发明名称 SUCCESSIVE COMPARISON TYPE A/D CONVERTER
摘要 PROBLEM TO BE SOLVED: To obtain a successive comparison type A/D converter where a measurement time of an input leakage characteristic is reduced. SOLUTION: A channel selector 3 connects to switches T0-T7 and the channel selector 3 outputs analog input terminal selection signals SL0-SL7 respectively to the switches T0-T7. Furthermore, input signal lines are connected in common to a sample-and-hold circuit 2. The sample-and-hold circuit 2 is provided with a capacitor CT whose one electrode connects to ground, a switch TT that selects conduction/non-conduction between the capacitor CT and the input signal lines, and a mode changeover circuit MO connecting to the switch TT. The mode changeover circuit MO selects an ON/OFF sate of the switch TT. Furthermore, the mode changeover circuit MO receives a sampling signal SMP and a test mode signal SLT.
申请公布号 JP2000134096(A) 申请公布日期 2000.05.12
申请号 JP19980306149 申请日期 1998.10.27
申请人 NEC CORP 发明人 TERAO MITSUKO
分类号 H03M1/10;H03M1/38;(IPC1-7):H03M1/10 主分类号 H03M1/10
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