| 摘要 |
PROBLEM TO BE SOLVED: To decrease the ON resistance in a junction-type field effect transistor and to improve the withstand pressure between a gate region and a source drain region. SOLUTION: In this manufacturing method, an n-type source region 2 and a drain region 3 are selectively formed on a semiconductor substrate 1. An n-type channel region 4 is formed between those regions. A recess part is formed in an interlayer insulating film on the semiconductor substrate 1. Through this recess part, p-type impurity Mg ions are injected into the channel region 4, and an n- type channel low-concentration region 5 is formed. A side wall 11 is formed at the part of the upper interlayer insulating film 7 of the channel region 4, and an opening part 11a is formed. Through the opening part 11a, p-type impurity Zn is diffused into the channel region 4, and a p-type gate region 6 is formed. After a gate electrode 12 is formed through the opening part 11a, a source electrode 13 and a drain electrode 14 are formed.
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