发明名称 MASK AND MANUFACTURE OF SEMICONDUCTOR DEVICE USING IT
摘要 <p>PROBLEM TO BE SOLVED: To enhance superposing accuracy in a lithography process executed after a substrate flattening process by chemical and mechanical polishing technique by arranging a mark pattern at a position where the density of the peripheral transmitting pattern of the mark pattern becomes almost symmetric with respect to the mark pattern. SOLUTION: The mark pattern for positioning used when another mark pattern is positioned and transferred by being superposed on the mark pattern transferred on a substrate is arranged at the position where the density of the peripheral transmitting pattern of the mark pattern becomes almost symmetric with respect to the mark pattern. For example, chips 10-1 and 10-2 whose layout are identical are arranged side by side in an exposure shot 3. Then, a mark pattern for an aligner used for positioning in the case of superposing exposure, a pattern for inspecting superposing deviation used for measuring positional deviation in the case of the superposing exposure, another pattern for inspection and a QC pattern are arranged in an area 11 other than the chips 10-1 and 10-2 which is normally called scribe area.</p>
申请公布号 JP2000131826(A) 申请公布日期 2000.05.12
申请号 JP19980304991 申请日期 1998.10.27
申请人 HITACHI LTD 发明人 IMAI AKIRA;NAKAMURA YOSHITAKA;YOSHIDA MAKOTO;HASEGAWA NORIO
分类号 H01L21/027;G03F1/42;G03F1/70;(IPC1-7):G03F1/08 主分类号 H01L21/027
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