| 摘要 |
PROBLEM TO BE SOLVED: To suppress jitters of a binary signal to its minimum with respect to a clock signal by controlling an asymmetry level to minimize phase errors of a data PLL(Phase Locked Level) for generating the clock signal synchronous with the binary signal generated in an asymmetry circuit. SOLUTION: An RF signal is converted into a binary signal PLDT by a compactor 21 and a phase error is detected by a phase error detection circuit 32 between the binary signal PLAT and a clock signal PLUCK synchronous therewith. A phase error signal outputted from the phase error detection circuit 32 is sorted into the phase error signal at the rising edge of the binary signal PLAT and the phase error signal at the falling edge thereof by a phase error sorting circuit 24 and a current flows by a charge pump 22 based on the phase error signals sorted to be converted into a DC voltage by an integration circuit 23. Thus, the voltage is fed back to an input of the comparator 21 as asymmetry level. |
