| 摘要 |
<p>A memory cell array comprising static memory cells, wherein preamplifiers which receive the signals of the memory cells read out on complementary bit line pairs and main amplifiers which receive the output signals of the preamplifiers are provided. The number of the memory cells connected to the complementary bit lines is limited so that the amplitudes of the signals which are supplied to the inputs of the preamplifier and read out on the bit line pairs may be larger than those of the output signals of the preamplifiers.</p> |
