METHOD AND APPARATUS FOR PROVIDING A PIPELINED MEMORY CONTROLLER
摘要
A piplined memory controller (105) that includes a decode stage, and a schedule stage, wherein the schedule stage includes a command queue (121, 123) to store multiple commands. In one embodiment, the schedule stage further includes look ahead logic (114) which can modify an order. Memory commands are stored in the command queue.
申请公布号
WO0026744(A2)
申请公布日期
2000.05.11
申请号
WO1999US25640
申请日期
1999.11.01
申请人
INTEL CORPORATION;NIZAR, PUTHIYA, K.;WILLIAMS, MICHAEL, W.
