| 摘要 |
<p>A hierarchical word line driving structure uses a shared inverter circuit architecture which allows for lower power consumption and a pulsed control signal to ensure accurate memory retrieval. The shared inverter word line structure includes a row decoder, a first sub-word line driver, a second sub-word line driver, and an interconnect line. The first sub-word line driver includes an inverting circuit for inverting the signal propagating along the global word line, while the second sub-word line driver does not. The interconnect line is coupled between the first and second sub-word line drivers to communicate the inverted signal therebetween. A pulsed control signal is supplied to clamping transistors connected to unselected word lines to ensure they remain clamped to ground.</p> |
