| 摘要 |
A variable clock divider circuit is provided. The variable clock divider circuit receives an input clock signal and generates an output clock signal having an output clock frequency that is less than the input clock frequency of the input clock signal. In one embodiment, a controller generates a rising-edge control signal and a falling-edge control signal. An output generator drives rising edges on the output clock signal in response to active edges on the rising-edge control signal. Conversely, the output generator drives falling edges on the output clock signal in response to active edges on the falling-edge control signal. The frequency of the rising-edge control signal and the frequency of the falling-edge control signal are variable. Common settings for the frequency of the rising-edge control signal and the falling-edge control signal include the frequency of the input clock signal divided by an integer.
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