Altering bit sequences to contain predetermined patterns

摘要

A low-overhead scheme for built-in self-test of digital designs incorporating scan allows for complete (100%) fault coverage without modifying the function logic and without degrading system performance (beyond using scan). By altering a pseudo-random bit sequence with bit-fixing logic at an LFSR's serial output, deterministic test cubes that detect random pattern-resistant faults are generated. A procedure for synthesizing the bit-fixing logic allows for complete fault coverage with low hardware overhead. Also, the present approach permits the use of small LFSR's for generating the pseudo-random bit sequence. The faults that are not detected because of linear dependencies in the LFSR can be detected by generating more deterministic cubes at the expense of additional bit-fixing logic.