发明名称 |
Planarization on an embedded dynamic random access memory |
摘要 |
A planarization method used in fabricating an embedded dynamic random access memory (DRAM). After a number of metal-oxide semiconductor (MOS) transistors and a number of capacitors are formed on a semiconductor substrate, a first inter-layer di-electric (ILD) layer is formed over the substrate. The embedded DRAM is divided into a memory region and a logic region. Next, planarization is performed. A dummy metal layer is formed and coupled to an interchangeable source/drain region of the MOS transistor in the logic region. Then a second ILD layer is formed over the logic region to compensate difference in height between the logic region and the memory region. Then, a via hole/plug is formed in the logic region to extend the first metal layer. A second metal layer with required contact window/plugs is formed over the substrate.
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申请公布号 |
US6060349(A) |
申请公布日期 |
2000.05.09 |
申请号 |
US19980152449 |
申请日期 |
1998.09.14 |
申请人 |
UNITED MICROELECTRONICS CORP. |
发明人 |
PENG, TZU-MIN;HUANG, KEH-CHING;CHEN, TUNG-PO;JUNG, TZ-GUEI |
分类号 |
H01L21/8242;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/8242 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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