| 摘要 |
PCT No. PCT/DE97/00407 Sec. 371 Date Sep. 14, 1998 Sec. 102(e) Date Sep. 14, 1998 PCT Filed Mar. 4, 1997 PCT Pub. No. WO97/34254 PCT Pub. Date Sep. 18, 1997The invention relates to a chip card having a card body (2) and a semiconductor chip (3) which is accommodated within the card body (2) and on which a control circuit (7) and a semiconductor memory device, which is electrically coupled to the control circuit (7), are constructed in an integrated manner, which control circuit (7) is supplied with a supply voltage generated by a voltage supply circuit (12) and with a clock generated by a clock supply circuit (13), which is arranged separately from the control circuit (6). The control circuit (7) of the semiconductor chip (3), which is accommodated within the card body (2), is assigned a sensor circuit (14) which detects a deviation of the allowed operating state of the control circuit (7) and, if a disallowed operating state of the control circuit is present, generates a triggering signal which is fed to a triggering circuit (18), which is connected downstream of the sensor circuit (14), is assigned to the semiconductor memory device and, as a reaction to the triggering signal, controls an at least partial erasure of the data content of memory cells of the semiconductor memory device.
|
