发明名称 |
Modeling and processing of on-chip interconnect capacitance |
摘要 |
An apparatus and method is presented for capacitance analysis in chip environments for arbitrary geometries. It uses a process which combines 2-dimensional ascertainments where the length is chosen to fit the solution. Also, the required accuracy may be limited to be within an error range. The technique is also applicable for the analysis of three dimensional capacitances, and importantly also for a mixture of two and three dimensional capacitance ascertainments. In an embodiment the process divides the space into a set of subspaces. The capacitance value for the subspaces are determined using the parallel plate capacitance formula.
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申请公布号 |
US6061508(A) |
申请公布日期 |
2000.05.09 |
申请号 |
US19970888060 |
申请日期 |
1997.07.03 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
MEHROTRA, SHARAD;NARASIMHAN, JAGANNATHAN;RUEHLI, ALBERT EMIL |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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