发明名称 |
Semiconductor memory device having a multibit test mode |
摘要 |
In a predetermined multibit test mode, a multibit test circuit 114 issues determination result data pairs RDM0 and /RDM0 to RDM3 and /RDM3, each of which corresponds to match/mismatch of logics of data read from memory cells selected by one column select line in corresponding one of memory cell plane blocks. In each memory cell plane block, memory cell columns selected by one single column select line can be replaced as a unit. The unit of memory cell columns containing a defective memory cell is replaced in accordance with determination result data RDM0 and /RDM0 to RDM3 and /RDM3.
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申请公布号 |
US6061808(A) |
申请公布日期 |
2000.05.09 |
申请号 |
US19990332364 |
申请日期 |
1999.06.14 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
YAMAUCHI, TADAAKI;ASAKURA, MIKIO;ITO, TAKASHI |
分类号 |
G11C11/401;G11C29/00;G11C29/04;G11C29/34;(IPC1-7):G01R31/28;G06F11/00 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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