| 摘要 |
An audio decoder is described that can concurrently produce two synchronized outputs of a digital audio stream at different sampling rates and can provide for seamless switching between the rates. In one embodiment, the audio decoder includes a first output buffer, an arithmetic logic unit (ALU), a second output buffer, and a control module. The first audio buffer is configured to buffer a sequence of digital audio samples and to provide the first sequence of digital audio samples to an output device at 96 kHz. The arithmetic logic unit (ALU) is coupled to the first output buffer to retrieve the first sequence of digital audio samples and to convert the first sequence of digital audio samples into a decimated sequence of digital audio samples. The second output buffer is coupled to the ALU to buffer the decimated sequence of digital audio and to provide the decimated sequence of digital audio samples to a second output device at 48 kHz. The control module receives a sample request signal at 96 kHz and responsively provides first and second address signals to the first and second output buffers, respectively, to indicate which digital audio samples are next provided to the output devices. In one implementation of this, the control module implements a first state machine to determine the first address signal and a second, separate state machine to determine the second address signal. This advantageously maintains close synchronization between the two output streams with minimal hardware requirements.
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