| 摘要 |
A divider circuit provides a divide operation with a multiplier, counter and comparator. The divide operation of two values, x and y, to produce the value of x divided by y, x/y, is provided by sequentially multiplying y in the multiplier with values from the counter until the product of y and a current counter value is determined to cross a unity level, or "1," as determined by a comparator. Therefore, the current value in the counter is approximately equal to 1/y. Then, the determined value of 1/y is multiplied by x to provide x/y. A preferred embodiment of the divider circuit employs a single multiplier, and the divide circuit includes a mux, a multiplier, a counter, a comparator, and an optional buffer. The mux receives two values x and y and a selection signal provided by the comparator. The counter is loaded with an initial value, which may be a zero dataword. The selection signal of the comparator initially causes the mux to provide the value of y, the optional buffer to provide a null output value, and the counter to be enabled. The counter provides sequential counter values in accordance with transitions of a counter clock. When the counter value corresponds to 1/y, the selection signal of the comparator changes state, freezing the value in the counter and causing the mux to provide the value of x. Consequently, the frozen value of the counter is multiplied with x to provide x/y. The optional buffer receives the output of the multiplier and may also be enabled by the selection signal having the changed state and an external control signal.
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