| 摘要 |
Custom circuitry for an adaptive, RAM-based, hardware routing engine conforms bit selection dynamically to information made available by a self-optimizing data hashing algorithm. Circuitry includes a staggered multiplexor array for selecting bits from only the most distinctive bit positions of an inbound identifier to effectuate associative comparisons at approximately CAM speeds under perfect or near perfect hash conditions. The custom circuitry includes means for monitoring routing performance and instructing a processing element to correct the hashing algorithm when performance has sufficiently deteriorated. The custom circuitry also has an extended recursive look-up capability.
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