Generation of reproducible random initial states in RTL simulators

摘要

The inventive mechanism generates reproducible random initial states for use in simulation testing a design of a logic machine. The mechanism uses the hierarchical path names for the modules of the design and a random seed to generate reproducible random initialization states. Since the path names and the seed are known quantities, the random number can be reproduced. This allows the logic designs to be tested by different simulation methods and still have the same initialization states. Furthermore, if the simulation fails, design changes can be verified by using the same initialization states which caused the failure.