Logic circuit emulator

摘要

An apparatus for simulating a logic circuit is disclosed comprising a first plurality of logic block circuits for simulating portions of the logic circuit the logic block circuits having a predetermined number of inputs and outputs; at least one routing logic block for routing signals between the logic block circuits; each of the logic block circuits further including: a first series of output scan chain units for capturing and storing each of the signal outputs of a corresponding the logic block circuit; and a second series of input scan chain units for storing and inputting a signal to each of the logic block inputs; each of the scan chain units being further interconnected to the routing logic block for the storing of the input signals and the output signals to and from the routing logic block. Further, the scan chain units can preferably comprise a series of serially interconnected storage units and the interconnection of the routing logic can preferably comprise a serial interconnection between one of the storage units and the routing logic. Ideally, the storage units comprise flip flops each interconnected to a master clock signal input. The output scan chain units can include a multiplexer connected between the signal outputs and a corresponding storage unit the multiplexer multiplexing the signal output and the output of an adjacent storage unit.