发明名称 |
Shielded bit line sensing scheme for nonvolatile semiconductor memory |
摘要 |
A memory incorporates a shield bit line reading system for fixing one of two bit lines disposed adjacent to each other to a shield potential and reading data to the other bit line. Selected bit lines are precharged to a power source potential, and then brought to a floating state. The shield bit lines are fixed to the power source potential. A period in which the power source potential is applied to the selected bit lines and a period in which the power source potential is applied to the shield bit lines are the same. A source line decoder applies the power source potential to sources of NAND cell units connected to selected bit lines and applies a ground potential to sources of NAND cell units connected to shield bit lines. Then, an output of data is produced from the memory cell to the selected bit lines.
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申请公布号 |
US6058044(A) |
申请公布日期 |
2000.05.02 |
申请号 |
US19980207929 |
申请日期 |
1998.12.09 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
SUGIURA, YOSHIHISA;IWATA, YOSHIHISA;WATANABE, HIROSHI |
分类号 |
G11C16/02;G11C16/04;G11C16/26;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):G11C16/04 |
主分类号 |
G11C16/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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