发明名称 |
Integrated circuit memory devices having reduced power consumption requirements during standby mode operation |
摘要 |
Integrated circuit memory devices (e.g., SDRAM) include an input buffer and a power reduction control circuit which disables the input buffer in response to an inactive chip select signal (CSB). The input buffer comprises a first differential amplifier having a first input electrically coupled to an input signal line (PX) and a first pull-up transistor electrically connected in series between a pull-up reference node of the first differential amplifier and a power supply signal line (e.g., Vcc). The output of the power reduction control circuit is electrically connected to a gate electrode of the first pull-up transistor. The first pull-up transistor can be turned off in response to an inactive chip select signal (CSB=1), to thereby electrically disconnect the first differential amplifier from its power supply. The input buffer may also comprise a first pull-down transistor electrically connected in series between an output of the first differential amplifier and a reference potential signal line (e.g., GND) and the output of the power reduction control circuit is electrically connected to a gate electrode of the first pull-down transistor.
|
申请公布号 |
US6058063(A) |
申请公布日期 |
2000.05.02 |
申请号 |
US19980187544 |
申请日期 |
1998.11.06 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
JANG, HYUN-SOON |
分类号 |
G11C11/409;G11C7/10;G11C11/407;G11C11/413;H01L21/8238;H01L27/092;H03K19/0175;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/409 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|