发明名称 |
CIRCUIT FOR ZERO-RUN DEVELOPING RUN/LEVEL SETS AND METHOD FOR ZERO-RUN DEVELOPING THE SAME |
摘要 |
<p>A zero-run developing circuit for performing a zero-run developing process for placing zeros represented by a run between first non-zero data and second non-zero data of a block of a predetermined number of run-length signals, each of which is composed of the level of the value of non-zero data and the run that is the number of zero-data followed by the non-zero data is disclosed, that comprises a latch circuit for latching the levels of the predetermined number of the non-zero data, a first write position generating circuit for generating a first latch position of the latch circuit at which the first non-zero data is written corresponding to a first run length signal, and a second write position generating circuit for generating a second latch position of the latch circuit at which the second non-zero data is written corresponding to the first run-length signal and a second run-length signal. <IMAGE></p> |
申请公布号 |
KR100255062(B1) |
申请公布日期 |
2000.05.01 |
申请号 |
KR19960004089 |
申请日期 |
1996.02.21 |
申请人 |
NEC CORPORATION |
发明人 |
KINOUCHI, SHIGENORI;SAWADA, AKIRA |
分类号 |
G06T9/00;H03M7/46;H04N19/423;H04N19/436;H04N19/44;H04N19/60;H04N19/91;H04N19/93;(IPC1-7):H04N7/52 |
主分类号 |
G06T9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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