| 摘要 |
PURPOSE: A decoding circuit of a flash memory is provided to use a global row decoder, increase the number of local row decoders receiving the output of the global row decoder when dividing sectors in column direction as well as to minimize the loading of row address path to reduce the chip size. CONSTITUTION: The decoding circuit of the flash memory includes a global row decoder and a local row decoder. The global row decoder includes the first through forth transistors(T1,T2,T3,T4). The first and second transistors are operated with response to a XnCOM signal. The global row decoder receives the voltage transmitted by the operation of the first and second transistors. The third and forth transistors are operated with response to the translated voltage. The global row decoder outputs the voltage applied on Vppx or Veex to the global word line. The local row decoder includes fifth through seventh transistors. The local row decoder receives the global word line. The fifth through seventh transistors are operated with response to the first and second column sector address. The local row decoder outputs the voltage of the global word line to the word line.
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