MULTIPLIER FOR 2'S COMPLEMENT COMPLEX NUMBER

摘要

PURPOSE: A two's complement complex multiplier is provided to perform an operation of a complex multiplier with one multiplier by generating a determined control signal using a data clock of the complex multiplier and a clock two times faster than the clock, by time-dividing and operating the multiplier through the control signal. CONSTITUTION: The first clock is connected to a data input terminal(D1) of the first D-flipflop(102). The second clock is connected to an input terminal of an inverter(101). An output terminal of the first D-flipflop(102) is connected to a data input terminal(D2) of the second D-flipflop(103). An output terminal of the inverter(101) is connected to clock apply terminals of the first D-flipflop(102) and the third D-flipflop(103). The second clock is connected to a clock apply terminal of the second D-flipflop(103). The first clock is used as the first input control signal. An output of the first D-flipflop is commonly used as the second input control signal and the first time division control signal. An output of the second D-flipflop(103) is used as the second time division control signal. An output of the third D-flipflop(104) is used as the third time division control signal.