发明名称 ADDRESS GENERATION CIRCUIT AND METHOD FOR DIGITAL SIGNAL PROCESSOR
摘要 PURPOSE: A circuit and method for creating an address of a digital signal processor is provided to facilitate an access with respect to a memory of a two dimensions array by adding a multiplier and directly creating an address of the corresponding area in accessing a predetermined area of another column after accessing a predetermined area of one column. CONSTITUTION: The first register(210) stores a row value(Di2) of a memory of a two dimensions array. A multiplier(220) multiplies wanted column value(Di3) of a memory of two dimensions array by the row value(Di2) stored in the first register(210). A multiplexer(230) selects and outputs one out of the output value of the multiplier(220), input data and a reference value. A calculating logic(240) adds or subtracts a previous address to the reference value in the multiplexer(230) in case that a specific area address of wanted array is created by calculating a successively selected an output value in the multiplexer(230) and the input data(Di) and a row direction area are successively selected from the specific address of the array. The second register(250) stores an output signal of the calculating logic(240) and outputs to the current address and feeds back the signal into the calculating logic(240).
申请公布号 KR100253182(B1) 申请公布日期 2000.05.01
申请号 KR19970018538 申请日期 1997.05.13
申请人 LG ELECTRONICS INC. 发明人 PARK, JONG BUM
分类号 G06F12/02;(IPC1-7):G06F12/02 主分类号 G06F12/02
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