| 摘要 |
PURPOSE: An SRAM cell circuit for low power consumption is provided to reduce the whole load of a word line by connecting the word line to a latch through one transistor , thereby operating the device with low power consumption. CONSTITUTION: According to the structure of the SRAM cell circuit, a bit line(BL) is connected to one terminal of a latch(11) through a pass NMOS transistor(NM11), and another terminal of the latch is connected to a bit line(BLB) through a pass NMOS transistor(NM12), and then a word line(WL) is connected to gates of the NMOS transistors through a PMOS transistor(PM11) in common, and thus the connection point thereof is connected to a ground terminal through a resistor NMOS transistor(NM13), and a column selection line(CSL) is connected to a gate of the PMOS transistor.
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