DCT CORE CAPABLE OF MULTIPLYING OF WEIGHTING COEFFICIENTS ARCHITECTURE

摘要

PURPOSE: A discrete cosine conversion core structure capable of processing a weighting coefficient is provided to reduce the size of hardware by using memory in which a weighting coefficient is multiplied by a DCT coefficient in a DCT/IDCT core without a special multiplier. CONSTITUTION: An input module(30) outputs data signals of input matrices of 8*1 DCT/IDCT and 2*(4*1) DCT/IDCT mode. A 3*1 multiplexer(32) selects a data signal of the input matrix. A butterfly(34) performs an addition and a subtraction of the input matrix selected by the 3*1 multiplexer(32). A 2*1 multiplexer(36) selects a data signal of the input matrix selected by the 3*1 multiplexer(32). A memory module(50) stores an addition and a subtraction result between cosine coefficients of the data signals and a weighting coefficient. A 4*1 multiplexer(42) selects an output signal of the memory module(50). A bit serial adder(60) outputs an 8*1 DCT, a 2*(4*1) DCT and a 2*(4*1) IDCT result. A butterfly (62) performs an addition and a subtraction of the 8*1 DCT of the bit serial adder(60). A 2*1 multiplexer(64) selects an output of the butterfly(62) or an output of the bit serial adder(60). An output module(66) outputs the signal selected by the multiplexer(64).