| 摘要 |
PURPOSE: An ATM cell monitor circuit is provided to monitor the existence of a relevant cell having a VPI(Virtual Path Identifier) value for all VPI values in ATM cells having their respective VPI values for each channel in order to detect a continuity test cell or a user cell only in case that the relevant cell exists and to execute a continuity test for the cell. CONSTITUTION: An ATM cell monitor circuit is provided with a VPI latch part(11), the first multiplexer(12), an OR gate(13), an AND gate(14), the first RAM(15), the second multiplexer(16), the second RAM(17), a D flip-flop(18) and a counter(19). The VPI latch part(11) latches 8-bit data equivalent to a VPI value from an ATM cell of each channel and 3-bit data equivalent to the channel number of the ATM cell. The VPI latch part(11) inputs the upper-level 5-bit data of the 8-bit data and the 3-bit data to the D0 port of the first multiplexer(12) and the D0 ports of the second multiplexer(16) so as to be used as the address signal of the first RAM(15). The VPI latch part(11) decodes the lower-level 3-bit data into 8-bit data and supplies the data to the input port of the OR gate(13) so as to be used as the data of the first RAM(15). The first multiplexer(12) multiplexes an address signal inputted through the D0 port and an address signal outputted from the counter(9) and supplies them to the AL port of the first RAM(15). The OR gate(13) executes OR operation for the 8-bit data inputted from the VL port of the VPI latch part(11) and 8-bit data inputted from the output port(Q) of the D flip-flop(18) and inputs the operated data to the AND gate(14). The AND gate(14) executes AND operation for the 8-bit data and a clear signal inputted from the OR gate(13) and supplies them to the DL port of the first RAM(15). The first RAM(15) records the 8-bit data inputted through the DL port from the AND gate(14) according to the address signal through the AL port from the first multiplexer(12). The second multiplexer(16) multiplexes an address signal inputted through the DL port and an address signal outputted from the counter(9) and supplies them to the AR port of the second RAM(15).
|
