发明名称 SEMICONDUCTOR TEST DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor test device provided with a pattern generator which can generate easily a pattern corresponding to arrangement of a memory cell. SOLUTION: This device is provided with an address conversion means 350, first, generating successively even number address signals in which values of an address signals are doubled and outputting them, and generating successively odd number address signals in which values of an address signals are doubled and '1' is added to the result, and outputting them. Further the device is provided with a generated pattern reversing means 325 generating successively even inversion signals making one side of even number address signals from the address conversion means 350 as a function, reversing even number pattern signals generated by one side of a pattern generating means of pattern generating means of two systems by the even number inversion signals as the prescribed condition and outputting them, generating successively odd number inversion signals making the other side of odd number address signals from the address conversion means 350 as a function, reversing odd number pattern signals generated by the other side of a pattern generating means 350 of pattern generating means of two systems by the odd number inversion signals to the prescribed condition and outputting them.
申请公布号 JP2000123597(A) 申请公布日期 2000.04.28
申请号 JP19980299429 申请日期 1998.10.21
申请人 ADVANTEST CORP 发明人 OSAWA TOSHIMI
分类号 G01R31/3183;G01R31/3181;G01R31/319;G11C29/10;(IPC1-7):G11C29/00;G01R31/318 主分类号 G01R31/3183
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