| 摘要 |
PROBLEM TO BE SOLVED: To provide a buffer circuit capable of suppressing the increase of delay time even when the capacity of a load connected to an output terminal is increased. SOLUTION: In this buffer circuit, the base terminal of a P channel transistor 36 is connected to a power source 28 in the case input signals are at an L level and the base terminal of the P channel transistor 36 is connected to an output terminal 38 in the case the input signals are at an H level. In the meantime, the base terminal of an N channel transistor 37 is connected to the output terminal 38 in the case the input signals are at the L level and the base terminal of the N channel transistor 37 is connected to a ground 35 in the case the input signals are at the H level.
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