发明名称 DRAM REFRESH CONTROL CIRCUIT AND DRAM INCORPORATING REFRESH CONTROL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To extend the backup time by limiting the region to be backed up to an absolute minimum during a power interruption in the refresh control of a DRAM. SOLUTION: A portion of the region, in which picture information is stored, among the entire region of a DRAM 1 is specified 2 by row addresses. Then, a refresh period 3 is set to the period that is proportional to the reciprocal of the percentage of the refresh range among all row addresses so that refresh operations are executed with a sufficient frequency for a memory holding and the condition of the data is maintained.
申请公布号 JP2000123568(A) 申请公布日期 2000.04.28
申请号 JP19980291886 申请日期 1998.10.14
申请人 RICOH CO LTD 发明人 HAYASHI SHIGEO
分类号 G11C11/406;G11C11/403;(IPC1-7):G11C11/406 主分类号 G11C11/406
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