发明名称 SEMICONDUCTOR ALIGNER
摘要 PROBLEM TO BE SOLVED: To reduce the time for correcting the overlay slippage of patterns due to the individual difference of reticles when using separate reticles having the same pattern for the same device by using manufacturing error information every reticle as an offset of aligning the reticle pattern to a wafer. SOLUTION: Manufacturing errors against design values of each reticle are previously stored in a file 17. When the reticle is carried to a reticle stage 12, a controller 16 computes the offset of a focused point of a reticle alignment scope 31, focuses on a reticle alignment mark, and aligns this mark with a reticle reference mark. The controller 16 refers to the file 7 to take out the manufacturing errors and moves the wafer stage 15 with the manufacturing error difference taken as an offset so that a circuit pattern of the reticle overlays a circuit pattern of the wafer below a projection lens 14.
申请公布号 JP2000124125(A) 申请公布日期 2000.04.28
申请号 JP19980317014 申请日期 1998.10.21
申请人 CANON INC 发明人 KUSUMOTO HIROSHI
分类号 H01L21/027;G03F9/00;(IPC1-7):H01L21/027 主分类号 H01L21/027
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