| 摘要 |
<p>PROBLEM TO BE SOLVED: To select the optimum timing corresponding to a frequency of an external clock signal and to fetch an input signal by generating the clock signal of the prescribed timing according to a clock selection signal, synchronizing with the clock signal and fetching the input signal. SOLUTION: A mode register 27 of a memory interface part 300 receives setting information from a system device side mounting a semiconductor device 100, and sends the clock selection signal CLKSEL to a clock control part 21 of an input/output interface part 200 according to the frequency of the external clock signal CLK. Thus, the clock control part 21 generates respectively the reverse signal of the external clock signal CLK, or the signal delaying the external clock signal CLK by a fixed time as an internal clock signal INCLK according to the case where the frequency of the external clock signal CLK is higher or lower than a prescribed reference, and supply the reverse signal to input signal fetch circuits 23.</p> |
