发明名称 CHIP-SIZE PACKAGE AND ITS MANUFACTURE
摘要 <p>PROBLEM TO BE SOLVED: To provide a chip-size package and its manufacture, which can make a highly accurate electrical connection between a bump and a wiring pattern and obtain both bump-pitch reduction and bump-strength improvement, and which are high in mass-productivity by forming a bump array into a multilayered structure. SOLUTION: A bump array 2 of a 1st layer and an insulating layer 3 are formed on a semiconductor chip 1, the bump array 2 of the 1st layer is exposed in the insulating layer 3, and a bump array 5 of a 2nd layer is formed on a wiring pattern 4 on the insulating layer 5 and is electrically connected to the bump array 2 of the 1st layer. If the material for the insulation layer is set as light-transmissive resin, the semiconductor chip is able to have a wiring pattern formed, while optically positioning faces up through photolithography, and the bump arrays and wiring pattern can be positioned with high accuracy. When the bumps of the 2nd layer are made larger in size than those of the bumps of the 1st layer, improvements in both the bump-pitch reduction and bump-strength improvement can be made.</p>
申请公布号 JP2000124354(A) 申请公布日期 2000.04.28
申请号 JP19980299859 申请日期 1998.10.21
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YAMAGUCHI KAZUFUMI;TATEISHI FUMIKAZU
分类号 H01L23/12;H01L21/60;(IPC1-7):H01L23/12 主分类号 H01L23/12
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