发明名称 RECEPTION SYNCHRONOUS PROTECTION SETTING METHOD FOR RADIO BASE STATION
摘要 <p>PROBLEM TO BE SOLVED: To maintain synchronization establishment by resetting the position in a first synchronous word detection window of a second synchronous word detection window at prescribed conditions. SOLUTION: A CPU 3 decides whether or not a calculated bit error rate matches the reset condition of a second synchronous word detection window generating part 8 stored in a memory 16. The result is written in a second synchronous word detection window generation part reset register of a synchronous register 7 as reset data. The CPU 3 calculates the bit error rate in an N frame, at any time from the number of errors of a synchronous word SW. When conditions which exceed synchronous word bit error rate X% is satisfied, reset of the second synchronous word detection window generation part 8 is performed through an AP2 generation part reset register of the synchronous part register 7. At this time, a generation position of the second synchronous detection window AP2 is changed with a synchronous word detection pulse(d) position in a second synchronous word detection window AP 2 as a reference.</p>
申请公布号 JP2000124854(A) 申请公布日期 2000.04.28
申请号 JP19980297479 申请日期 1998.10.20
申请人 FUJITSU LTD 发明人 MARUTANI KENICHI
分类号 H04J3/06;H04B7/26;H04L7/08;H04Q7/10;H04Q7/20;(IPC1-7):H04B7/26 主分类号 H04J3/06
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