| 摘要 |
PROBLEM TO BE SOLVED: To eliminate a partial writing access to a common memory at the time of a cache writing mishit when pertinent data against a writing request does not exist in a cache memory. SOLUTION: A CPU module provided with CPU 1 and cache memories 2, 3, 4 and 5 is provided with a register 7 for merging writing data of CPU 1 and reading data from a main memory. Thus, transfer between CPU 1 and the memories becomes the block transfer of arranged data width and the number of arranged words without fail, and the availability of system buses 9a-9d is improved. Thus, the reading modifying writing access of the memories is unnecessitated. Then, processing speed at the time of the cache mishit writing is accelerated.
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