| 摘要 |
PROBLEM TO BE SOLVED: To carry out circuit extrapolation readily by executing automatic layout of a cell base in a place wherein a logic gate is not arranged, and adding an upper layer wiring to a transistor cell based on connection information during re-design when circuit extrapolation is required. SOLUTION: In an automatic layout system of a cell base, transistor cell arrangement information is provided to a place wherein a logic gate is not arranged. When timing error in actual delay simulation and functional trouble of a sample are generated and circuit extrapolation is required, logic/connection information for circuit extrapolation is added to connection information. Circuit extrapolation is realized just by adding an upper layer wiring to a transistor cell arranged in advance in a mask manufacturing process based on connection information during redesign. As a result, dummy cell shortage can be eliminated by carrying out circuit extrapolation by constituting a logic gate.
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