发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To make tuning of an oscillation frequency characteristic easy by installing plural pairs of oscillation means which are different in adjustment means, frequency division means and the oscillation frequency characteristics. SOLUTION: A phase comparator 11 compares a phase of a clock to be inputted to a phase-locked loop(PLL) circuit with that of a frequency division clock and controls a pulse width of a pulse signal A to be supplied to a charge pump 12. The charge pump 12 adjusts the control voltage of a voltage-controlled oscillator 14 (VCO), a low pass filter 13 eliminates a high frequency noise in the control voltage, and the VCO 14 oscillates a clock of a frequency corresponding to the control voltage. A phase comparator 21 compares the phase of an external clock to be inputted to the PLL circuit with that of a frequency division clock B, controls the pulse width of a pulse signal B to be supplied to a charge pump 22, the charge pump 22 adjusts a control voltage of a VCO 24, and an LPF 23 eliminates the high-frequency noise in the control voltage. The VCO 24 has an oscillation frequency characteristic which is different from the VCO 14 and oscillates a clock of a frequency corresponding to the control voltage.
申请公布号 JP2000124802(A) 申请公布日期 2000.04.28
申请号 JP19980298494 申请日期 1998.10.20
申请人 MITSUBISHI ELECTRIC CORP 发明人 SHIMOMURA TAKEHIKO
分类号 H03L7/087;H03L7/07;H03L7/089;H03L7/18;H03L7/22;H03L7/23 主分类号 H03L7/087
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