Output buffer has MOS transistor with low potential node connected to control node of pull-up transistor and high potential nodes connected to low potential node of another transistor and high potential supply line

摘要

Input and output terminals of a delay stage (IV2) such as NOT gate are connected to input node (INPUT) and control (MOS transistor) node of MOS current regulator (M6) respectively. The diode arrangement has low potential node connected to control node of pull-up transistor (M3) and high potential node connected to low potential node of MOS stromreglar current regulator (M6) and another high potential node connected to high potential supply line. A pull-up transistor (M3) has a control node, a high potential node and a low potential node connected to input node (INPUT), high potential supply line and output node (OUTPUT) respectively. A pull-down transistor (M4) has a control node, high potential node, low potential node connected to input node, output node and low potential supply line respectively. The clamping circuit (20) comprises the NOT gate (IV2) and MOS transistor (M5,M6). An Independent claim is also included for signal disturbances reducing method.