| 摘要 |
PROBLEM TO BE SOLVED: To facilitate synthesis by controlling input timing and addressing to a memory and compositing and outputting image data such as a still picture and continuous images in which a vertical synchronizing signal is inputted asynchronously, a vertical scan frequency is different and a horizontal scan frequency is equal. SOLUTION: A line gate detecting device 16 detects the line gate marker of image data outputted from each memory, nullifies the address counter of the detected memory and stops horizontal image data display at the position. Also, when both 1st and 2nd or 3rd respective memories 9 and 10 or 15 detect it, the address counter is made effective again. A synthesis deciding device 17 compares image data outputted from the 1st memory 9 with a preliminarily set luminance level in every pixel, a D/A converter 12 convert the data in each pixel unit when it is equal to or more than a set value and converts the data of the 2nd or 3rd memory 10 or 15 when it is below the set value, and a synchronizing signal and a blank signal are superimposed on the data in the timing of an output of a timing controller 11 to be a composited image signal. |
