METHOD AND APPARATUS FOR DE-JITTERING ASYNCHRONOUS DATA TRANSFER DELAY

摘要

A buffer-level based, nonlinear, second order phase-lock-loop (PLL) approach to synchronizing cells or packets which arrive having bounded but arbitrarily distributed packet transfer delay variation due to asynchronous transfer mode (ATM) or asynchronous multiplexing is disclosed. A recovery circuit for controlling clock timing at a receiver that receives asynchronous data includes a pair of cascaded buffers and a clock recovery unit. The clock recovery unit monitors the buffer level of the first buffer and the buffer level of the second buffer and controls clock timing for the first and second buffers in response to the first and second buffer levels, respectively.