发明名称 |
Process for manufacturing electronic devices comprising non-salicidated nonvolatile memory cells, non-salicidated HV transistors, and salicidated-junction LV transistors |
摘要 |
The process permits the manufacture of LV transistors (80) with salicidated junctions on first areas (19) of a substrate (2), HV transistors (81) on second areas (14) and memory cells (82) on third areas (13). The process comprises the steps of: forming LV oxide regions (36) and LV gate regions (43a) on the first areas (19), HV oxide regions (34) on the second areas (14), selection oxide regions (34), tunnel oxide regions (26b) and matrix oxide regions (25b) on the third areas (13); forming floating gate regions (27b) and insulating regions (31b) on the tunnel oxide regions and the matrix oxide regions; forming first LV source and drain regions (55) laterally to the LV gate regions (43a); forming suicide regions (75a1, 75a2) on the first source and drain regions (55) and on the LV gate regions (43a); forming semiconductor material regions (43) completely covering the second and third areas (13, 14); and at the same time forming HV gate regions (43d) on the HV oxide regions, selection gate regions (43c) on the selection oxide regions and control gate regions (43b) on the insulating regions through a step of shaping the semiconductor material regions. <IMAGE> |
申请公布号 |
EP0996152(A1) |
申请公布日期 |
2000.04.26 |
申请号 |
EP19980830644 |
申请日期 |
1998.10.23 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
PATELMO, MATTEO;DALLA LIBERA, GIOVANNA;GALBIATI, NADIA;VAJANA, BRUNO |
分类号 |
H01L21/8247;H01L27/105;H01L27/115;H01L29/788;H01L29/792 |
主分类号 |
H01L21/8247 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|