EEPROM with common control gate and common source for two cells

摘要

The electronic device comprises pairs of memory cells (61a, 61b), formed in a same active area (9) of a substrate (2) of semiconductor material. Each cell is formed by a selection transistor (63a, 63b) and by a memory transistor (64a, 64b) of the floating gate and double polysilicon layer type. The memory transistors (64a, 64b) of the coupled cells have control gate regions formed by a single continuous gate region (43c) of semiconductor material extending over the respective floating gate regions (30a, 30b) and on the sides thereof which are reciprocally face-to-face, and on the zone of the substrate (2) accommodating a common source line (28). <IMAGE>