发明名称 |
Method for encapsulating a metal via in damascene |
摘要 |
Disclosed is a method for encapsulating a via over a first metal layer of a semiconductor substrate in a damascene processing to prevent voiding. The method includes forming an intermetal oxide (IMO) layer over the first metal layer and forming a via in the IMO layer such that the via exposes a portion of the first metal layer and a side wall of the via in the IMO layer. The method also includes conformally forming a first barrier layer over the IMO layer and the via such that a portion of the first barrier layer is deposited over the side wall of the IMO layer and the exposed portion of the first metal layer. The method further includes depositing a second metal layer over the first barrier layer such that the second metal layer fills the via within the first barrier layer portion deposited in the via to form a metal via. Additionally, the method includes removing the second metal layer and the first barrier layer above a top portion of the IMO layer and forming a trench in a portion of the IMO layer in contact with the first barrier layer to a specified depth. The method further includes forming a second barrier layer in the trench. The method also forming a third metal layer over the second barrier layer in the trench to form a metal trench such that the metal via is encapsulated by the first barrier layer so as to reduce electromigration effect in the metal via.
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申请公布号 |
US6054378(A) |
申请公布日期 |
2000.04.25 |
申请号 |
US19980104753 |
申请日期 |
1998.06.25 |
申请人 |
VLSI TECHNOLOGY, INC. |
发明人 |
SKALA, STEPHEN L.;BOTHRA, SUBHAS |
分类号 |
H01L21/768;H01L23/522;H01L23/532;(IPC1-7):H01L21/476 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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