| 摘要 |
PURPOSE: A PLL(phase locked loop) circuit is provided to rapidly charge up/down the potential of the output of charge pump(CP) in period having large phase difference between input and output clocks and operate only first PFD and CP in period having small phase difference, thereby speed up lock time. CONSTITUTION: A PLL circuit comprises a first phased frequency divider(PFD), a second PFD, a first charge pump(CP) and a second CP. The first PFD forms a narrow dead zone period which does'n't detect phase difference between an input clock(CLK) and a feedback clock(CLK). The second PFD forms a wider dead zone period which does'n't detect phase difference between the input clock(CLK) and the feedback clock(CLK). The first CP is connected to the first PFD and consists of a transistor having small ON current. The second CP is connected to the second PFD and consists of a transistor having large ON current.
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