发明名称 Single chip clock control circuit operating independently of CPU control
摘要 It is an object to prevent peak power consumption occurring on transition from normal mode to a small power consumption mode. A control-signal generating circuit (4) controls an oscillation circuit (2) and control circuits (3A) and (3B) to realize three types of clock modes including the normal mode in which both of clocks (MC) and (PC) are supplied, a wait mode as a small power consumption mode in which only the clock (PC) is supplied and a stop mode as another small power consumption mode in which supply of both of the clocks (MC) and (PC) is interrupted. Control input signals (EI) and (SI) for instructing to control the control-signal generating circuit (4) are not allowed to pass through a CPU (5) and directly supplied from an ICU (6) in response to the external request signals (ERA) and (ERB). Since the transition to the small power consumption mode does not require the operation of the CPU (5), the peak power consumption can be prevented.
申请公布号 US6055642(A) 申请公布日期 2000.04.25
申请号 US19980115507 申请日期 1998.07.15
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 IKEMOTO, MASAHIKO
分类号 G06F1/04;G06F1/32;G06F15/78;(IPC1-7):G06F1/32 主分类号 G06F1/04
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