| 摘要 |
A delay cell for use in binary delay line which includes a delay circuit having N outputs where N>/=2, each delay circuit coupled to an input through N-1 serially connected unit cells. For each output there are P unit cells having a unit delay of tP0 and N-1-P unit cells having a unit delay of tp1. The N outputs are ordered such that each output other than the first is delayed with respect to an immediately preceding output by tp1-tp0, and P goes in succession from N-1 to 0 in unit steps. Each value of P corresponds to only one of the N outputs.
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