发明名称 |
Architecture for a dual segment dual speed repeater |
摘要 |
The present invention concerns a method and architecture comprising a first circuit, a second circuit, and a logic circuit coupled to said first and second circuits. The first segment generally comprises a first repeater core configured to operate at one of a plurality of speeds and a first port. The second segment generally comprises a second repeater core configured to operate at one of a plurality of speeds and a second port. A logic circuit may be configured to couple each of the first and second ports to either the first or second repeater core.
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申请公布号 |
US6055241(A) |
申请公布日期 |
2000.04.25 |
申请号 |
US19970970059 |
申请日期 |
1997.11.13 |
申请人 |
CYPRESS SEMICONDUCTOR CORP. |
发明人 |
RAZA, S. BABAR;TALAAT, M. MAGDY;WANG, YUN-CHE;KASPER, MICHAEL J. |
分类号 |
H04L12/56;(IPC1-7):H04L12/413 |
主分类号 |
H04L12/56 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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