| 摘要 |
In the early half of one period of a main clock, one multiplexer selects a signal Ain, while the other multiplexer selects an inverted signal /Ain. Consequently, the signal Ain is transmitted to a signal line assigned to the signal line Ain, while the signal /Ain is transmitted to a signal line assigned to a signal Bin, thereby accomplishing differential transmission of the signal Ain. In the late half of one period of the main clock, the above one multiplexer selects an inverted signal /Bin, while the above other multiplexer selects the signal Bin. Consequently, the inverted signal /Bin is transmitted to the signal line assigned to the signal Ain, while the signal Bin is transmitted to the signal line assigned to the signal Bin, thereby accomplishing differential transmission of the signal Bin. Since differential transmission is thus accomplished with no increase in the number of wires, power saving can be achieved by data transfer with a small amplitude.
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