发明名称 |
Memory cell |
摘要 |
A circuit that may be used as a memory cell that may be capable of a differential write and a single ended read. The circuit generally comprises a memory storage element having a write bitline, a complement write bitline and a read bitline. One or more first gates may be configured to pass data on the write bitline and the inverted write bitline during a write operation. The write operation may occur in response to a write control signal. A second gate may be configured to pass data on from the storage element to the read bitline in response to read control signal. As a result, the circuit may be written by both the write bitline and the complement write bitline and may be read by the read bitline.
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申请公布号 |
US6055177(A) |
申请公布日期 |
2000.04.25 |
申请号 |
US19980105724 |
申请日期 |
1998.06.26 |
申请人 |
CYPRESS SEMICONDUCTOR CORP. |
发明人 |
NARAYANA, PIDUGU L.;CRESS, DANIEL E.;HAWKINS, ANDREW L.;SAVAGE, DERRICK |
分类号 |
G11C8/16;(IPC1-7):G11C11/00 |
主分类号 |
G11C8/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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