Low power multiplexer circuit

摘要

A multiplexer circuit that provides output data signal transitions only for valid input data signals. The multiplexer includes pass gate devices and latches responsive to valid input data signals. A logic circuit responsive to a first, slow select binary input signal and a second, fast select binary input signal provides an output gating signal when the first and second binary input signals are present in the same binary state. Each pass gate device is connected to a separate input data signal from a data signal source. The pass gate devices are also connected to the output gating signal from the logic circuit such that the pass gate devices are gated and pass the input data signals in response to an output gating signal from the logic circuit upon the occurrence of the first and second binary input signals being in the same binary state. The input data signals passed by the pass gate devices are connected to latch circuits that latch and provide output signals in response to valid data signals passed through the pass gate devices.